This invention relates to synchronization of an oscillator output to a pulse train and, more particularly, to a method and apparatus for synchronizing an oscillator to a bunched, i.e., pulse-swallowed, or rapidly jittering pulse train.
In communications systems, there are a number of applications in which it is necessary to generate a smooth, i.e., regularly occurring, pulse train from a bunched, i.e., pulse-swallowed, or rapidly jittering pulse train. For example, pulse-swallowed data might result after error correction of a data stream or removal of framing codes. Recovering a low-jitter clock from such pulse-swallowed data can be a challenge, particularly in applications that require the capability of generating a range of clock frequencies. If CMOS technology is used in a communications system, clock recovery is additionally hampered by the high self-noise inherent in CMOS oscillators.
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train.
According to a feature of the invention, the oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The phase shifted signals are generated by the respective stages such that each stage produces two signals shifted in phase by 180xc2x0 from each other.
According to another feature of the invention, the output signal is compared with the bunched pulse train in a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal.
According to another feature of the invention, the phase shifted signal generating oscillator is incorporated into a phase locked loop so it can be synchronized to a single fixed frequency reference. The phase locked loop has a number of counters that can be programmed to change the frequency of the phase shifted signal generating oscillator. As a result, a smooth pulse train can be generated from a pulse-swallowed or rapidly jittering pulse train occurring over a wide range of frequencies.